KSOEM
Articles
- Page Path
- HOME > Ann Occup Environ Med > Volume 23(3); 2011 > Article
- Original Article Review on Potential Risk Factors in Wafer Fabrication Process of Semiconductor Industry
- Dong Uk Park, Hyae Jeong Byun, Sang Jun Choi, Jee Yeon Jeong, Chung Sik Yoon, Chi Nyon Kim, Kwon Chul Ha, Doo Yong Park
-
DOI: https://doi.org/10.35371/kjoem.2011.23.3.333
Published online: September 30, 2011
1Korea National Open University, Korea. pdw545@knou.ac.kr 
2Graduate School of Public Health, Seoul National University, Korea.
3Catholic University of Daegu, Korea.
4Yongin University, Korea.
5Graduate School of Public Health, Yonsei University, Korea.
6Changwon National University, Korea.
7Hansung University, Korea.
2Graduate School of Public Health, Seoul National University, Korea.
3Catholic University of Daegu, Korea.
4Yongin University, Korea.
5Graduate School of Public Health, Yonsei University, Korea.
6Changwon National University, Korea.
7Hansung University, Korea.
- 29 Views
- 2 Download
- 13 Crossref
- 0 Scopus
Abstract
OBJECTIVES
To associate work in the semiconductor industry, including silicon wafer fabrication, with cancer risks or mortality and other adverse health effects, the operation of wafer fabrication should initially be understood. A detailed study on the fabrication operation allows retrospective exposure to be assessed and wafer fabrication workers to be classified into similar exposure groups. Therefore, the objective of this study was to comprehensively review silicon wafer fabrication operations and related hazardous materials and agents.
METHODS
The literatures related to semiconductor industry processes were reviewed from an occupational health viewpoint based on wafer manufacturing, wafer fabrication and packaging. The focus was especially related to the hazardous materials used in wafer fabrication industries.
RESULTS
During the fabrication of silicon wafers, many toxic chemicals, a strong electric field and hazardous equipment are used. The process allows the integration of a three-dimensional array of electric circuits onto a silicon wafer substrate. Wafers are sliced from single crystal silicon and subject to a series of steps during the fabrication process, which alternatively adds and then selectively removes materials in layers from the surface of the wafer to create different parts of the completed integrated circuit. There are four major steps in this process; patterning, junction formation, thin film and metallization.
CONCLUSIONS
In order to associate exposure to the hazard agents generated during wafer fabrication operations with adverse health effects the details of the operation should be completely studied, which will be helpful in both exposure assessments and epidemiological studies.
Cite
